IBM's Power6 Chip Doubles speed, Consumes Same Energy

Today IBM officially announced its Power6 chip, claiming that the next-generation microprocessor for its Unix and Linux systems offers double the performance of the earlier Power5+ device while consuming roughly the same amount of electricity. IBM's new POWER6 chip is a 64 bit, dual-core processor with 790 million transistors running at up to 4.7 GHz and eight megabytes of on chip Level 2 cache.

The dramatic performance boost comes as the semiconductor industry has largely shifted its focus away from pure performance measurements and instead has become more concerned with a balance of performance and power consumption. Overheating becomes a major problem as transistors shrink and operate at breakneck speed. The trend among microprocessor makers is to focus on using multicore chips and throughput gains from techniques such as parallel processing to boost performance, instead of ratcheting up clock speeds. But with the Power6, IBM is working to keep both the multicore and clock speed avenues open.

The chip, which operates at 4.7GHz and cycles at a speed 25 million times as fast as the flap of hummingbird wings, will allow businesses to consolidate servers and handle substantially larger workloads. By comparison, Intel's Itanium 2 server processor tops out at 1.66GHz.

But the doubling of processing speed from the 2.2GHz Power5+ to the 4.7GHz Power 6 won't be the only reason that users upgrade to the new dual-core chip, predicted Ross Mauri, general manager of IBM's System p business unit. Companies will be able to move existing workloads to Power6-based systems and cut the energy use of their servers almost in half, Mauri said.

The Power6 will be generally available within two weeks in a new midrange server, called the System p 570, that can support up to eight physical processor sockets, for a total of 16 cores. The p 570 will run IBM's AIX version of Unix as well as Red Hat Linux and SUSE Linux, and it will be aimed at server consolidation or database and application server uses.

IBM's Breakthrough in Computer Chip Manufacturing

(Photo Courtesy: IBM )

Today IBM announced the first-ever application of a breakthrough self-assembling nanotechnology to conventional chip manufacturing, borrowing a process from nature to build the next generation computer chips.

Self assembly is a concept scientists have been studying at IBM and in labs around the world as a potential technique to create materials useful for building computer chips. The concept occurs in nature every day, it is how enamel is formed on our teeth, the process that creates seashells and is what transforms water into complex snowflakes. The major difference is, while the processes that occur in nature are all unique, IBM has been able to direct the self-assembly process to form trillions of holes that are all similar.

Today, chips are manufactured with copper wiring surrounded by an insulator, which involves using a mask to create circuit patterns by beaming light through the mask and later chemically removing the parts that are not needed. The new technique to make airgaps by self-assembly skips the masking and light-etching process. Instead IBM scientists discovered the right mix of compounds, which they pour onto a silicon wafer with the wired chip patterns, then bake it.

In the new method, IBM researchers coated a mixture of two polymers over the top of a silicon wafer. The two types of molecules in the coating, which were created from scratch by the scientists using component chemicals, then assembled themselves into a thin film pocked with evenly-spaced holes that contain no air. These vacuum spaces, sized 20 nanometers across and spaced 40 nanometers apart, act like molecule-sized versions of the vacuum tubes that once helped insulate mainframe computers and televisions.

This new form of insulation, commonly referred to as “airgaps” by scientists, is a misnomer, as the gaps are actually a vacuum, absent of air. A vacuum is believed to be the ultimate insulator for what is known as wiring capacitance, which occurs when two conductors, in this case adjacent wires on a chip, sap or siphon electrical energy from one another, generating undesirable heat and slowing the speed at which data can move through a chip. The technique deployed by IBM causes a vacuum to form between the copper wires on a computer chip, allowing electrical signals to flow faster, while consuming less electrical power. The self-assembly process enables the nano-scale patterning required to form the gaps; this patterning is considerably smaller than current lithographic techniques can achieve.

In chips running in IBM labs using the technique, the researchers have proven that the electrical signals on the chips can flow 35% faster, or the chips can consume 15% less energy compared to the most advanced chips using conventional techniques.

The IBM patented self-assembly process thus moved a nanotechnology manufacturing method that had shown promise in laboratories into a commercial manufacturing environment for the first time, providing the equivalent of two generations of Moore's Law wiring performance improvements in a single step, using conventional manufacturing techniques.

IBM said it completed a successful demonstration of the process in a run at its East Fishkill, N.Y., chip fabrication plant, and plans to use the new self-assembly method, in commercial-scale, server-chip production lines by 2009.